Transactions on Semiconductor Manufacturing , May 1995 - An Interactive VLSI CAD Tool for Yield Estimation

The yield of a VLSI chip depends, among other factors, on the sensitivity of the chip to defects occurring during the fabrication process. To predict this sensitivity, one usually needs to compute the so-called critical area (A c) which reeects how many and how large the defects must be in order to result in a circuit failure. The main computational problem in yield estimation is to calculate A c eeciently for complicated, irregular layouts. A novel approach is suggested for this problem that results in an algorithm that will solve it eeciently. This paper provides an interactive accurate and fast method for the rapid evaluation of critical area as a design tool with good visual feedback to allow layout improvement for higher yield. The algorithm is compared to other yield-prediction methods, which use either the Monte-Carlo approach (VLASIC) or a deterministic approach (SCA), and is shown to be faster. It also has the advantage that it can graphically show a detailed`defect sensitivity map' that can assist a chip designer in improving the yield of his/her layout. 3 YMAP { Computing the defect-sensitivity S() and the critical area A c. : : 15 4 Transforming an open-circuit problem to an analogous short-circuit problem. 16 5 Analysis of a cell for open-circuit fault sensitivity (left) and short-circuit fault sensitivity 6 Examples of sensitivity maps produced by YMAP for various layout conng-8 Two implementations of NAND with diierent wiring schemes and the cor-10 The WP-logic with improved wiring cell with its sensitivity map.